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LTC3425 1 3425f features applicatio s u descriptio u n handheld computers n point-of-load regulators n 3.3v to 5v conversion , ltc and lt are registered trademarks of linear technology corporation. n high efficiency: up to 95% n up to 3a continuous output current n 4-phase operation for low output ripple and tiny solution size n output disconnect and inrush current limiting n very low quiescent current: 12 m a n 0.5v to 4.5v input range n 2.4v to 5.25v adjustable output voltage n adjustable current limit n adjustable, fixed frequency operation from 100khz to 2mhz per phase n synchronizable oscillator with sync output n internal synchronous rectifiers n manual or automatic burst mode ? operation n power good comparator n <1 m a shutdown current n antiringing control n 5mm 5mm thermally enhanced qfn package 5a, 8mhz, 4-phase synchronous step-up dc/dc converter burst mode is a registered trademark of linear technology corporation. the ltc ? 3425 is a synchronous, 4-phase boost converter with output disconnect capable of operation below 1v input. it includes four n-channel mosfet switches and four p-channel synchronous rectifiers for an effective r ds(on) of 0.045 w and 0.05 w , respectively. 4-phase operation greatly reduces peak inductor currents, and capacitor ripple current, and increases effective switching frequency, minimizing inductor and capacitor sizes. true output disconnect eliminates inrush current and allows zero load current in shutdown. external schottky diodes are not required in most applications (v out < 4.3v). power saving burst mode operation can be user controlled or left in automatic mode. other features include 1 m a shutdown current, program- mable frequency with sync in and out, programmable soft-start, antiringing control, thermal shutdown, adjust- able current limit, reference output and power good comparator. the LTC3425 is available in a small, thermally enhanced 32-pin qfn package. 2.7 h 2.2 f 0.01 f 75k 15k 20k 2.7 h 2.7 h 2.7 h c in : taiyo yuden jmk107bj225ma c out : taiyo yuden jmk212bj475mg ( 4) l1-l4: tdk rlf5018t-2r7m1r8 v in swa v in 2v to 3v swb LTC3425 swc swd sgnd shdn off on v outs v outa v outb v outc v outd refout ccm refen syncin burst r t i lim pgood syncout ss fb comp gnda gndb gndc gndd 330pf 22pf 3425 ta01 4.7 f 4 0.01 f 33k 590k 1m 10k v out 3.3v 2a load current (ma) 0.1 70 efficiency (%) 80 90 1 10 100 1000 10000 3425 ta02 60 50 40 30 20 10 0 100 v in = 2.4v v out = 3.3v f = 1mhz/phase l = 2.7 h burst mode operation fixed frequency mode typical applicatio u
LTC3425 2 3425f parameter conditions min typ max units minimum start-up voltage v out = 0v, i load < 1ma 0.88 1 v minimum operating voltage (note 3) l 0.5 v output voltage adjust range l 2.4 5.25 v feedback regulation voltage l 1.196 1.220 1.244 v feedback input current 150 na v out quiescent currentburst mode operation burst = 0v, refen = 0v, fb = 1.3v (note 2) 12 25 m a burst = 0v, refen = 2v, fb = 1.3v (note 2) 18 35 m a v in quiescent currentshutdown shdn = 0v, v out = 0v, not including switch leakage 0.1 1 m a v out quiescent currentactive v c = 0v, nonswitching (note 2) 1.8 3 ma nmos switch leakage v sw = 5v 0.1 5 m a pmos switch leakage v sw = 5v, v out = 0v 0.1 10 m a nmos switch on resistance (note 4) 0.04 w pmos switch on resistance (note 4) 0.05 w nmos current limit i lim resistor = 75k (note 4) l 5.0 7.0 a i lim resistor = 200k (note 4) l 1.8 2.7 a v in voltage ................................................. C 0.3v to 6v swa-d voltages ..........................................C 0.3v to 6v v outa-d , v outs voltages............................ C 0.3v to 6v burst, shdn, ss, refen, syncout, pgood, refout, ccm, syncin voltages ............... C 0.3v to 6v operating ambient temperature range (note 5) .............................................. C 40 c to 85 c storage temperature range ................. C 65 c to 125 c lead temperature (soldering, 10 sec).................. 300 c order part number consult ltc marketing for parts specified with wider operating temperature ranges. LTC3425euh absolute axi u rati gs w ww u package/order i for atio uu w (note 1) t jmax = 125 c, q ja = 40 c/w 1 layer board, q ja = 35 c/w 4 layer board, q jc = 1.1 c/w exposed pad is gnd (pin 33) must be soldered to pcb 32 31 30 29 28 27 26 25 9 10 11 12 top view 33 uh package 32-lead (5mm 5mm) plastic qfn 13 14 15 16 17 18 19 20 21 22 23 24 8 7 6 5 4 3 2 1 gnda gnda swa v outa v outb swb gndb gndb gndd gndd swd v outd v outc swc gndc gndc ss shdn syncin v in r t i lim ccm syncout refen v outs sgnd fb comp burst refout pgood electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 1.2v, v out = 3.3v, r t = 15k, unless otherwise noted. uh part marking 3425
LTC3425 3 3425f parameter conditions min typ max units pmos turn-off current ccm < 0.4v C80 ma pmos reverse current limit ccm > 1.4v 0.6 a max duty cycle l 83 90 97 % min duty cycle l 0% frequency accuracy r t = 15k l 0.8 1 1.2 mhz shdn input high v out = 0v (initial start-up) l 1v v out > 2.4v l 0.65 v shdn input low l 0.25 v shdn input current v shdn = 5v or 0v 0.01 1 m a v shdn = 2v C0.50 m a refen, ccm input high l 1.4 v refen, ccm input low l 0.4 v refen, input current v refen = 5v 0.01 1 m a syncin input high (note 7) l 2.5 v syncin input low (note 7) l 0.5 v syncin input current v syncin = 5v 0.3 1 m a ccm input current v ccm = 5v 2 4 m a sync input pulse width range l 0.1 m s sync out high 3v sync out low 0.4 v refout refen > 1.4v, no load l 1.190 1.220 1.251 v i source < 100 m a, i sink < 10 m a l 1.184 1.220 1.252 v error amp transconductance 50 m s error amp output high i lim resistor = 75k 2.2 v error amp output low 0.15 v pgood threshold (falling edge) referenced to feedback voltage l C9.5 C11.4 C13.5 % pgood hysteresis referenced to feedback voltage l 1.5 2.5 4 % pgood low voltage i sink = 1ma (10ma max) l 0.12 0.25 v pgood leakage v pgood = 5.5v l 0.01 1 m a ss current source v ss = 1v 2.7 m a burst threshold voltage falling edge l 0.84 0.94 1.04 v burst threshold hysteresis 120 mv electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 1.2v, v out = 3.3v, r t = 15k, unless otherwise noted. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: current is measured into the v outs pin since the supply current is bootstrapped to the output. the current will reflect to the input supply by v out /(v in ? efficiency). the outputs are not switching. note 3: once the output is started, the ic is not dependent on the v in supply. note 4: total with all four fets in parallel. note 5: the LTC3425e is guaranteed to meet performance specifications from 0 c to 70 c. specifications over the C40 c to 85 c operating temperature range are assured by design, characterization and correlation with statistical process controls. note 6: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125 c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. note 7: the typical logic threshold for this input is: v out /2
LTC3425 4 3425f typical perfor a ce characteristics uw swa, swb, swc, swd at 1mhz/phase sw pin and oscillator syncout sw pin and inductor current in discontinous mode. antiring circuit eliminates high frequency ringing transient response 0.5a to 1.5a fixed frequency mode operation output voltage ripple at 2.5a load with only four 4.7 m f ceramic capacitors soft-start and inrush current limiting burst mode operation swa to swd 5v/div 250ns/div 3425 g01 swa 2v/div 250ns/div 3425 g02 syncout 2v/div v in = 2.4v 250ns/div 3425 g03 v out = 3.3v c out = 220 m f i l 0.2a/div sw 2v/div v in = 2.4v 100 m s/div 3425 g04 v out = 3.3v c out = 220 m f v out ac 100mv/div load current 0.5a/div v in = 2.4v 500ns/div 3425 g05 v out = 3.3v frequency = 1mhz/phase v out ac 50mv/div output voltage ripple at 2.5a load with a 47 m f ceramic bulk capacitor v in = 2.4v 500ns/div 3425 g06 v out = 3.3v frequency = 1mhz/phase v out ac 10mv/div v in = 2.4v 500 m s/div 3425 g07 v out = 3.3v c softstart = 0.015 m f i in 0.5a/div ss pin 1v/div v out 2v/div v in = 2.4v 25 m s/div 3425 g08 v out = 3.3v c out = 220 m f swa 2v/div v out ac 50mv/div transient response 10ma to 1a automatic burst mode operation v in = 2.4v 1ms/div 3425 g10 v out = 3.3v c out = 220 m f i out 1a/div burst pin 1v/div v out ac 200mv/div
LTC3425 5 3425f typical perfor a ce characteristics uw converter efficiency for v out = 3.3v converter efficiency for 2-, 3- and 4-phase operation efficiency comparison of discontinuous mode and forced continuous mode at light loads for v in = 2.4v, v out = 3.3v converter no load input current vs v in (burst mode operation) oscillator frequency peak current limit output current (ma) 0.1 1 70 efficiency (%) 80 90 10 100 1000 10000 3425 g11 60 50 40 30 20 10 0 100 v in = 2.4v v in = 1.2v v in = 1.2v v in = 2.4v t a = 25 c burst mode operation 1mhz/phase output current (ma) 0.1 1 70 efficiency (%) 80 90 10 100 1000 10000 3425 g12 60 0 10 20 30 40 50 100 t a = 25 c v in = 3.3v v in = 3.3v v in = 2.4v v in = 2.4v burst mode operation 1mhz/phase converter efficiency for v out = 5v load (ma) 100 80 efficiency (%) 84 82 86 88 90 92 94 96 1000 10000 3425 g13 98 4 phase t a = 25 c v in = 2.4v v out = 3.3v 1mhz/phase 3 phase 2 phase converter output current (ma) 1 40 efficiency (%) 50 60 70 80 10 100 1000 3425 g14 30 20 10 0 90 100 t a = 25 c 1mhz/phase discontinuous mode forced continuous mode load (ma) 1 40 efficiency (%) 50 60 70 80 10 100 1000 3425 g15 30 20 10 0 90 100 t a = 25 c 1mhz/phase discontinuous mode forced continuous mode efficiency comparison of discontinuous mode and forced continuous mode at light loads for v in = 3.3v, v out = 5v v in (v) 1.5 140 120 100 80 60 40 20 0 3.0 4.0 3425 g16 2.0 2.5 3.5 4.5 converter input current ( a) t a = 25 c v out = 3.3v v out = 5v r t (k ) 1 1 frequency (mhz) 10 10 100 3425 g17 t a = 25 c i lim resistor (k ) 60 peak current in each phase (a) 1.4 1.6 1.8 120 160 3425 g18 1.2 1.0 80 100 140 180 200 0.8 0.6 t a = 25 c effective r ds(on) v out (v) 2.5 r ds(on) (all four phases in parallel) 0.065 0.060 0.055 0.050 0.045 0.040 4.5 3425 g19 3 3.5 4 5 t a = 25 c pmos nmos
LTC3425 6 3425f typical perfor a ce characteristics uw maximum output current in burst mode operation v in (v) 1 1.5 output current (ma) 200 250 300 4 3425 g20 150 100 23 4.5 2.5 3.5 5 50 0 350 v out = 3.3v v out = 5v t a = 25 c v in (v) 0.9 0.4 0.5 0.7 1.2 1.4 3425 g21 0.3 0.2 1.0 1.1 1.3 1.5 1.6 0.1 0 0.6 load current (a) t a = 25 c v out = 3.3v v out = 5v maximum start-up load vs v in (constant current load) soft-start charging current vs temperature automatic burst mode current thresholds vs r burst burst resistor (k ) 10 1 average load current (ma) 10 100 100 1000 3425 g22 t a = 25 c enter burst mode operation leave burst mode operation v in (v) 1.5 load current (ma) 70 80 90 100 3.5 3425 g23 60 50 40 2 2.5 3 4 v out = 5v t a = 25 c r burst = 33k v out = 5v v out = 3.3v leave burst mode operation enter burst mode operation v out = 3.3v temperature ( c) ?5 0 ss charge current ( a) 0.5 1.0 1.5 2.0 3.0 ?5 5 15 35 75 55 3425 g24 95 115 2.5 v in > 2.3v v in < 2.3v (start-up mode) automatic burst mode thresholds vs v in pgood threshold vs temperature shutdown voltage vs temperature minimum start-up voltage vs temperature temperature ( c) ?5 0.300 shutdown voltage (v) 0.325 0.350 0.375 0.400 0.450 ?5 5 15 35 75 55 3425 g25 95 115 0.425 temperature ( c) ?5 0.70 start voltage (v) 0.75 0.80 0.85 0.90 1.00 ?5 5 15 35 75 55 3425 g26 95 115 0.95 temperature ( c) ?5 10.8 pgood threshold (1% below v fb ) 11.0 10.9 11.1 11.5 11.4 11.3 11.2 11.6 11.8 ?5 5 15 35 75 55 3425 g27 95 115 11.7 pmos reverse current in forced ccm vs temperature temperature ( c) ?5 300 pmos reverse current (ma) 400 350 450 650 600 550 500 700 800 ?5 5 15 35 75 55 3425 g28 95 115 750
LTC3425 7 3425f typical perfor a ce characteristics uw feedback voltage vs temperature peak current limit vs temperature error amplifier g m vs temperature oscillator frequency vs temperature burst mode v out quiescent current vs temperature temperature ( c) ?5 1.200 v fb (v) 1.205 1.210 1.215 1.220 1.230 ?5 5 15 35 75 55 3425 g29 95 115 1.225 temperature ( c) ?5 ? peak i lim (normalized) (%) ? ? 1 0 3 ?5 5 15 35 75 55 3425 g30 95 115 2 temperature ( c) ?5 2.0 oscillator (normalized) (%) ?.5 ?.0 0.5 1.0 0.5 0 2.0 ?5 5 15 35 75 55 3425 g31 95 115 1.5 temperature ( c) ?5 5 quiescent current ( a) 10 15 20 ?5 5 15 35 75 55 3425 g32 95 115 temperature ( c) ?5 40 g m ( s) 45 50 55 ?5 5 15 35 75 55 3425 g33 95 115
LTC3425 8 3425f pi fu ctio s uuu gndaCd (pins 1, 2, 7, 8, 17, 18, 23, 24): power ground for the ic and the four internal n-channel mosfets. connect directly to the power ground plane. swaCd (pins 3, 6, 19, 22): switch pins. connect induc- tors here. minimize trace length to keep emi to a mini- mum. for discontinuous inductor current, a controlled impedance is internally connected from sw to v in to minimize emi. for applications where v out > 4.3v, it is required to have schottky diodes from sw to v out or a snubber circuit to stay within absolute maximum rating on the sw pins. v outaCd (pins 4, 5, 20, 21): output of the four synchro- nous rectifiers. connect output filter capacitors to these pins. connect one low esr ceramic capacitor directly from each pin to the ground plane. refen (pin 9): pull this pin above 1.4v to enable the ref output. grounding this pin turns the ref output off to reduce quiescent current. v outs (pin 10): v out sense pin. connect v outs directly to an output filter capacitor. the top of the feedback divider network should also be tied to this point. sgnd (pin 11): signal ground pin. connect to ground plane, near the feedback divider resistor. fb (pin 12): feedback pin. connect fb to a resistor divider, keeping the trace as short as possible. the output voltage can be adjusted according to the following formula: v rr r out = + 122 12 1 . where r1 is connected from fb to sgnd and r2 is connected from fb to v outs . comp (pin 13): error amp output. a frequency compen- sation network is connected from this pin to ground to compensate the loop. see the section closing the feed- back loop for guidelines. burst (pin 14): burst mode threshold adjust pin. a resistor/capacitor combination from this pin to ground programs the average load current at which automatic burst mode operation is entered. for manual control of burst mode operation, ground burst to force burst mode operation or connect it to v out to force fixed frequency pwm mode. note that burst must not be pulled higher than v out . refout (pin 15): buffered 1.22v reference output. this pin can source up to 100 m a and sink up to 10 m a (only active when refen is pulled high). this pin must be decoupled with a 0.1 m f capacitor for stability. pgood (pin 16): open-drain output of the power good comparator. this pin will go low when the output voltage drops 11% below its regulated value. maximum sink current should be limited to 10ma. syncout (pin 25): sync output pin. a clock is provided at the oscillator frequency, but phase-shifted 180 degrees to allow for synchronizing two devices for an 8-phase converter. ccm (pin 26): this pin is used to select forced continuous conduction mode. normally this pin is grounded to allow ccm or dcm operation. to force continuous conduction mode, tie this pin to v out . in this mode, a reverse current of up to about 0.6a will be allowed before turning off the synchronous rectifier. this will prevent pulse skipping at light load when burst mode operation is disabled, and will also improve the large-signal transient response when going from a heavy load to a light load. for burst mode operation, ccm should be low.
LTC3425 9 3425f i lim (pin 27): current limit adjust pin. connect a resistor from i lim to sgnd to set the peak current limit threshold for the n-channel mosfets, according to the formula (note that this is the peak current in each inductor): i r lim = 130 where i is in amps and r is in k w . do not use values less than 75k. r t (pin 28): connect a resistor from r t to sgnd (or sgnd plane) to program the oscillator frequency, according to the formula: f r f f r osc t switch osc t = == 60 4 15 where f osc is in mhz and r t is in k w . v in (pin 29): input supply pin. connect this to the input supply and decouple with 1 m f minimum low esr ceramic capacitor. pi fu ctio s uuu syncin (pin 30): oscillator synchronization pin. a clock pulse width of 100ns minimum is required to synchronize the internal oscillator. if not used, syncin should be grounded. the typical logic threshold for this input is: v out 2 the syncin is ignored in burst mode operation. shdn (pin 31): shutdown pin. grounding shdn (or pulling it below 0.25v) shuts down the ic. pull pin up to 3 1v to enable. once enabled, the pin only needs to be 3 0.65v. ss (pin 32): soft-start pin. connect a capacitor from this pin to ground to set the soft-start time, according to the formula: t(ms) = c ss ( m f) ? 320 the nominal soft-start charging current is 2.5 m a. the active range of ss is from 0.8v to 1.6v. note that this is the rise time of ss. the actual rise time of v out will be a function of load and output capacitance. exposed pad (pin 33): additional power ground for the ic. connect directly to the power ground plane. operating mode burst pin ccm pin automatic burst (operating mode is load dependent) rc network to ground low forced burst low low forced fixed frequency with pulse skipping at light load high low forced fixed frequency, low noise (no pulse skipping) high high
LTC3425 10 3425f block diagra w s ?% 0.94v mode sleep v ref 3% sgnd gndd gndc gndb gnda + + burst mode control + + burst comp uv ov error amp start-up, soft-start and thermal reg i limit comp 1.22v 1.086/ 1.116 + + + + v ref 1.22v i lim 27 ss 32 burst 14 24 23 18 17 8 7 2 1 refout 15 refen shutdown 9 shdn syncout syncin sync off on 31 25 30 r t 28 ccm mode control pmos enable fb 0.8v + 11 33 thermal shdn 13 fb 12 pgood 16 v outs v out 2.5v to 5.25v 10 v outb 5 v outc 20 v outa 4 v outd 21 + slope divider 4-phase gen pwm logic and drivers antiring n p zero i/2000 1v to 4.5v 1 of 4 + osc iosc clk 4 4 26 swb 6 v in + swa 29 3 swc 19 swd 22 + s 4 4 4 + off on refout
LTC3425 11 3425f operatio u detailed description the LTC3425 provides high efficiency, low noise power for high current boost applications such as cellular phones and pdas. the true output disconnect feature eliminates inrush current and allows v out to go to zero during shutdown. the current mode architecture with adaptive slope compensation provides ease of loop compensation with excellent transient load response. the low r ds(on) , low gate charge synchronous switches eliminate the need for an external schottky rectifier, and provide efficient high frequency pulse width modulation (pwm) control. high efficiency is achieved at light loads when burst mode operation is entered, where the ics quiescent current is a low 12 m a typical on v out . multiphase operation the LTC3425 uses a 4-phase architecture, rather than the conventional single phase of other boost converters. by having multiple phases equally spaced (90 apart), not only is the output ripple frequency increased by a factor of four, but the output capacitor ripple current is greatly reduced. although this architecture requires four induc- tors, rather than a single inductor, there are a number of important advantages. ? much lower peak inductor current allows the use of smaller, lower cost inductors. ? greatly reduced output ripple current minimizes output capacitance requirement. ? higher frequency output ripple is easier to filter for low noise applications. ? input ripple current is also reduced for lower noise on v in . the peak boost inductor current is given by: i i dn di lpeak o =+ ( ) 12 where i o is the average load current, d is the pwm duty cycle, n is the number of phases and di is the inductor ripple current. this relationship is shown graphically in figure 1 using a single phase and a 4-phase example. example: the following example, operating at 50% duty cycle, illustrates the advantages of multiphase operation over a conventional single-phase design. v in = 1.9v, v out = 3.6v, efficiency = 90% (approx), i out = 2a, frequency = 1mhz, l = 2.2 m h table 1 single four change from parameter phase phase 1 to 4 phase peak-peak output 4.227a 0.450a reduced by 89% ripple current rms output ripple current 2.00a 0.184a reduced by 91% peak inductor current 4.227a 1.227a reduced by 71% output ripple frequency 1mhz 4mhz increased by 4 with 4-phase operation, at least one of the phases will be delivering current to the load whenever v in is greater than one quarter v out (duty cycles less than 75%). for lower duty cycles, there can be as many as two or three phases delivering load current simultaneously. this greatly re- duces both the output ripple current and the peak current in each inductor, compared with a single-phase converter. this is illustrated in the waveforms of figures 2 and 3. operation using only two or three phases the LTC3425 can operate as a 2- or 3-phase converter by simply eliminating the inductor from the unused phase(s). time ( s) 0 output ripple current (a) 2 four phase single phase 3 3425 f01 1 0 0.5 1 1.5 5 4 figure 1. comparison of output ripple current with single phase and 4-phase boost converter in a 2a load application operating at 50% duty cycle
LTC3425 12 3425f operatio u switch a voltage switch b voltage switch c voltage switch d voltage inductor a current inductor b current inductor c current inductor d current rectifier a current rectifier b current rectifier c current rectifier d current output ripple current input current 3425 f02 figure 2. simplified voltage and current waveforms for 4-phase operation at 50% duty cycle this approach can be used to reduce solution cost and board area in applications not requiring the full power capability of the LTC3425, or where peak efficiency may not be as important as cost and size. in this case, phase a should always be used, since this is the only phase active in burst mode operation and phase c is recommended as the second phase for the lowest output ripple, since it is 180 out of phase with phase a. figure 4 illustrates the efficiency differences with two, three and four phases in a typical 2-cell to 3.3v boost application. in this example, you can see that for maximum loads less than 1a, the efficiency penalty for using only two or three phases is fairly small. keep in mind, however, that this penalty will grow larger as the input voltage drops. output ripple will also increase with each phase that is eliminated. low voltage start-up the LTC3425 includes an independent start-up oscillator designed to start up at input voltages as low as 0.88v. the frequency and peak current limit during start-up are
LTC3425 13 3425f switch a voltage switch b voltage switch c voltage switch d voltage inductor a current inductor b current inductor c current inductor d current rectifier a current rectifier b current rectifier c current rectifier d current output ripple current input current 3432 f03 operatio u figure 3. simplified voltage and current waveforms for 4-phase operation at 75% duty cycle inter nally controlled. the device can start up under some load (see the graph start-up current vs input voltage). soft-start and inrush current limiting is provided during start-up as well as normal mode. the same soft-start capacitor is used for each operating mode. during start-up, all four phases switch in unison. when either v in or v out exceeds 2.3v, the ic enters normal operating mode. once the output voltage exceeds the input by 0.3v, the ic powers itself from v out instead of v in . at this point the internal circuitry has no dependency on the v in input voltage, eliminating the requirement for a large input capacitor. the input voltage can drop as low as 0.5v without affecting circuit operation. the limiting factor for the application becomes the ability of the power source to supply sufficient energy to the output at the low volt- ages, and the maximum duty cycle that is clamped at 90%.
LTC3425 14 3425f operatio u low noise fixed frequency operation shutdown: the part is shut down by pulling shdn below 0.25v and made active by pulling the pin above 1v. note that shdn can be driven above v in or v out , as long as it is limited to less than 5.5v. soft-start: the soft-start time is programmed with an external capacitor to ground on ss. an internal current source charges it with a nominal 2.5 m a (1 m a while in start- up mode when v in and v out are both below 2.3v). the voltage on the soft-start pin (in conjunction with the external resistor on the i lim pin) is used to control the peak current limit until the voltage on the capacitor exceeds 1.6v, at which point the external resistor sets the peak current. in the event of a commanded shutdown or a thermal shutdown, the capacitor is discharged automati- cally. note that burst mode operation is inhibited during the soft-start time. t(ms) = c ss ( m f) ? 320 oscillator: the frequency of operation is set through a re- sistor from the r t pin to ground. an internally trimmed timing capacitor resides inside the ic. the internal oscillator frequency is then divided by four to generate the four phases, each phase shifted by 90 . the oscillator fre- quency and resulting switching frequency of each of the four phases are calculated using the following formula: f r f f r osc t switch osc t = == 60 4 15 where f osc is in mhz and r t is in k w . the oscillator can be synchronized with an external clock applied to syncin. when synchronizing the oscillator, the free running frequency must be set to an approximately 30% lower frequency than the desired synchronized fre- quency. syncout is provided for synchronizing two or more devices. the output sync pulse is 180 out of phase from the internal oscillator, allowing two devices to be synchronized to create an 8-phase converter. note that in burst mode operation, the oscillator is turned off and syncout is driven low. in fixed frequency operation, the minimum on-time before pulse skipping occurs (at light load) is typically 110ns. current sensing: lossless current sensing converts the peak current signal to a voltage to sum in with the internal slope compensation. this summed signal is compared to the error amplifier output to provide a peak current control command for the pwm. the internal slope-compensation is adaptive to the input and output voltage, therefore the converter provides the proper amount of slope compensa- tion to ensure stability, but not an excess to cause a loss of phase margin in the converter. error amp: the error amplifier is a transconductance amplifier with its positive input internally connected to the 1.22v reference and its negative input connected to fb. a simple compensation network is placed from comp to ground. internal clamps limit the minimum and maximum error amp output voltage for improved large-signal tran- sient response. during burst mode operation, the com- pensation pin is high impedance, however clamps limit the voltage on the external compensation network, preventing the compensation capacitor from discharging to zero. figure 4. LTC3425 efficiency vs load for 2-, 3- and 4-phase operation load (ma) 100 80 efficiency (%) 84 82 86 88 90 92 94 96 1000 10000 3425 g13 98 4 phase t a = 25 c v in = 2.4v v out = 3.3v 1mhz/phase 3 phase 2 phase
LTC3425 15 3425f current limit: the programmable current limit circuit sets the maximum peak current in the nmos switches. the current limit level is programmed using a resistor to ground on the i lim pin. do not use values below 75k. in burst mode operation, the current limit is automatically set to a nominal value of 0.6a peak for optimal efficiency. i r lim = 130 per phase where i is in amps and r is in k w . synchronous rectifier and zero current amp: to pre- vent the inductor current from running away, the pmos synchronous rectifier is only enabled when v out > (v in + 0.3v) and fb is > 0.8v.the zero current amplifier monitors the inductor current to the output and shuts off the synchronous rectifier once the current is below 50ma typical, preventing negative inductor current. if ccm is tied high, the amplifier will allow up to 0.6a of negative current in the synchronous rectifier. antiringing control: the antiringing control connects a resistor across the inductor to damp the ringing on sw in discontinuous conduction mode. the lc sw ringing (l = inductor, c sw = capacitance on switch pin) is low energy, but can cause emi radiation. power good: an internal comparator monitors the fb voltage. if fb drops 11.4% below the regulation value, pgood will pull low (sink current should be limited to 10ma max). the output will stay low until the fb voltage is within 9.5% of the regulation voltage. a filter prevents noise spikes from causing nuisance trips. reference output: the internal 1.22v reference is buff- ered and brought out to refout. it is active when refen is pulled high (above 1.4v). for stability, a minimum of 0.1 m f capacitor must be placed on refout. the output can source up to 100 m a and sink up to 10 m a. for the lowest possible quiescent current in burst mode operation, the reference output should be disabled by grounding refen. thermal shutdown: an internal temperature monitor will start to reduce the programmed peak current limit if the die temperature exceeds 135 c. if the die temperature continues to rise and reaches 150 c, the part will go into thermal shutdown and all switches will be turned off and the soft-start capacitor will be reset. the part will be enabled again when the die temperature has dropped about 10 c. note: overtemperature protection is intended to protect the device during momentary overload condi- tions. continuous operation above the specified maxi- mum operating junction temperature may result in device degradation or failure. burst mode operation burst mode operation can be automatic or user controlled. in automatic operation, the ic will automatically enter burst mode operation at light load and return to fixed frequency pwm mode for heavier loads. the user can program the average load current at which the mode transition occurs using a single resistor. during burst mode operation, only phase a is active and the other three phases are turned off, reducing quiescent current and switching losses by 75%. note that the oscillator is also shut down in this mode, since the on time is determined by the time it takes the inductor current to reach a fixed peak current, and the off time is determined by the time it takes for the inductor current to return to zero. in burst mode operation, the ic delivers energy to the output until it is regulated and then goes into a sleep mode where the outputs are off and the ic is consuming only 12 m a of quiescent current. in this mode, the output ripple has a variable frequency component with load current and will be typically 2% peak-peak. this maximizes efficiency at very light loads by minimizing switching and quiescent losses. burst mode ripple can be reduced slightly by using more output capacitance (47 m f or greater). this capacitor does not need to be a low esr type if low esr ceramics are also used. another method of reducing burst mode ripple is to place a small feedforward capacitor across the upper resistor in the v out feedback divider network. during burst mode operation, comp is disconnected from the error amplifier in an effort to hold the voltage on the external compensation network where it was before entering burst mode operation. to minimize the effects of leakage current and stray resistance, voltage clamps limit the min and max voltage on comp during burst mode operation. this minimizes the transient experienced when operatio u
LTC3425 16 3425f a heavy load is suddenly applied to the converter after being in burst mode operation for an extended period of time. for automatic operation, an rc network should be con- nected from burst to ground. the value of the resistor will control the average load current (i burst ) at which burst mode operation will be entered and exited (there is hysteresis to prevent oscillation between modes). the equation given for the capacitor on burst is for the minimum value, to prevent ripple on burst from causing the part to oscillate in and out of burst mode operation at the current where the mode transition occurs. i r i r burst burst burst burst = = 275 17 . . to leave burst mode operation to enter burst mode operation where r burst is in k w and i burst is in amps. for load currents under 20ma, refer to the curve automatic burst mode thresholds vs r burst . c cv burst out out = , 10 000 where c burst(min) and c out are in m f. when the voltage on burst drops below 0.94v, the part will enter burst mode operation. when the burst pin voltage is above 1.06v, it will be in fixed frequency mode. in the event that a sudden load transient causes the feedback pin to drop by more than 4% from the regulation value, an internal pull-up is applied to burst, forcing the part quickly out of burst mode operation. for optimum transient response when going between burst mode operation and pwm mode, the mode should be controlled manually by the host. this way pwm mode can be commanded before the load step occurs, minimizing output voltage droop. for manual control of burst mode operation, the rc network can be eliminated. to force fixed frequency pwm mode, burst should be connected to v out . to force burst mode operation, burst should be grounded. the circuit connected to burst should be able operatio u to sink up to 2ma. note that burst mode operation is inhibited during start-up and soft-start. note that if v in is raised to within 200mv or less below v out , the part will exit burst mode operation and the synchronous rectifier will be disabled. it will remain in fixed frequency mode until v in is at least 300mv below v out . if the load applied during forced burst mode operation (burst = gnd) exceeds the current that can be supplied, the output voltage will start to droop and the part will automatically come out of burst mode operation and enter fixed frequency mode, raising v out . the part will then enter burst mode operation once again, the cycle will repeat, resulting in about 4% output ripple. the maximum current that can be supplied in burst mode operation is given by: i vv v in amps o max out in in () . = + ? ? ? ? 060 21 output disconnect and inrush limiting the LTC3425 is designed to allow true output disconnect by eliminating body diode conduction of the internal pmos rectifiers. this allows v out to go to zero volts during shutdown, drawing no current from the input source. it also allows for inrush current limiting at turn-on, minimizing surge currents seen by the input supply. note that to obtain the advantages of output disconnect, there cannot be any external schottky diodes connected be- tween the switch pins and v out . note: board layout is extremely critical to minimize voltage overshoot on the switch pins due to stray induc- tance. keep the output filter capacitors as close as possible to the v out pins, and use very low esr/esl ceramic capacitors tied to a good ground plane. for applications with v out over 4.3v, schottky diodes are required to limit the peak switch voltage to less than 6v. these must also be very close to minimize stray induc- tance. see the section applications where v out > 4.3v.
LTC3425 17 3425f component selection inductor selection the high frequency, multiphase operation of the LTC3425 allows the use of small surface mount inductors. the minimum inductance value is proportional to the operat- ing frequency and is limited by the following constraints: l f and l vv v f ripple v in min out max in min out max >> () 2 () ( ) () () where: f = operating frequency in mhz (of each phase) ripple = allowable inductor current ripple (amps peak-peak) v in(min) = minimum input voltage v out(max) = maximum output voltage the inductor current ripple is typically set to 20% to 40% of the maximum inductor current. for high efficiency, choose an inductor with high fre- quency core material, such as ferrite to reduce core loses. the inductor should have low esr (equivalent series resistance) to reduce the i 2 r losses, and must be able to handle the peak inductor current without saturating. to minimize radiated noise, use a shielded inductor. (note that the inductance of shielded types will drop more as current increases, and will saturate more easily). see table 2 for a list of inductor manufacturers. table 2. inductor vendor information supplier phone fax web site coilcraft (847) 639-6400 (847) 639-1469 www.coilcraft.com murata usa: usa: www.murata.com (814) 237-1431 (814) 238-0490 sumida usa: usa: www.japanlink.com/ (847) 956-0666 (847) 956-0702 sumida japan: japan: 81-3-3607-5111 81-3-3607-5144 tdk (847) 803-6100 (847) 803-6296 www.component. tdk.com some example inductor part types are: coilcraft do-1608, ds-1608 and dt-1608 series murata lqh3c, lqh4c, lqh32c and lqn6c series sumida cdrh3d16, cdrh4d18, cdrh4d28, cr32, cr43 series tdk rlf5018t and nlfc453232t series output capacitor selection the output voltage ripple has three components to it. the bulk value of the capacitor is set to reduce the ripple due to charge into the capacitor each cycle. the max ripple due to charge is given by: v iv cvf rbulk pin out out = 4 where: i p = peak inductor current f = switching frequency of one phase applicatio s i for atio wu uu LTC3425 l1 l2 l3 l4 3425 f05 c in c out c out c out c out c ss r t figure 5. typical board layout LTC3425 3425 f06 figure 6. example board layout for a 10w, 4-phase boost converter. total area = 0.50in 2 (with all components mounted on the topside of board)
LTC3425 18 3425f voltage from exceeding its maximum rating during the break-before-make time. surface mount diodes, such as the mbr0520l or equivalent, must be used and must be located very close to the pins to minimize stray inductance. two example application circuits are shown in figures 7 and 8, one with output disconnect and one without. operating frequency selection t here are several considerations in selecting the operat- ing frequency of the converter. the first is, which are the sensitive frequency bands that cannot tolerate any spec- tral noise? for example, in products incorporating rf communications, the 455khz if frequency is sensitive to any noise, therefore switching above 600khz is desired. some communications have sensitivity to 1.1mhz, and in that case, a 1.5mhz converter frequency may be employed. the second consideration is the physical size of the converter. as the operating frequency goes up, the induc- tor and filter capacitors go down in value and size. the trade off is in efficiency, since the switching losses in- crease proportionally with frequency. thermal considerations to deliver the power that the LTC3425 is capable of, it is imperative that a good thermal path be provided to dissi- pate the heat generated within the package. this can be accomplished by taking advantage of the large thermal pad on the underside of the ic. it is recommended that multiple vias in the printed circuit board be used to conduct heat away from the ic and into a copper plane with as much area as possible. in the event that the junction temperature gets too high, the peak current limit will automatically be decreased. if the junction temperature continues to rise, the part will go into thermal shutdown, and all switching will stop until the temperature drops. closing the feedback loop the LTC3425 uses current mode control with internal adaptive slope compensation. current mode control elimi- nates the 2nd order filter, due to the inductor and output capacitor exhibited in voltage mode controllers, and sim- plifies it to a single pole filter response. the product of the applicatio s i for atio wu uu the esr (equivalent series resistance) is usually the most dominant factor for ripple in most power converters. the ripple due to capacitor esr is given by: v rcesr = i p ? c esr where c esr = capacitor series resistance the esl (equivalent series inductance) is also an impor- tant factor for high frequency converters. using small, surface mount ceramic capacitors, placed as close as possible to the v out pins, will minimize esl. low esr/esl capacitors should be used to minimize output voltage ripple. for surface mount applications, avx tps series tantalum capacitors, sanyo poscap or x5r type ceramic capacitors are recommended. in all applications, a minimum of 1 m f, low esr ceramic capacitor should be placed as close to each of the four v out pins as possible, and grounded to a local ground plane. input capacitor selection the input filter capacitor reduces peak currents drawn from the input source and reduces input switching noise. since the ic can operate at voltages below 0.5v once the output is regulated (as long as shdn is above 0.65v), the demand on the input capacitor to lower ripple is much less. taiyo yuden offers very low esr capacitors, for example the 2.2 m f in a 0603 case (jmk107bj22ma). see table 3 for a list of capacitor manufacturers for input and output capacitor selection. table 3. capacitor vendor information supplier phone fax web site avx (803) 448-9411 (803) 448-1943 www.avxcorp.com sanyo (619) 661-6322 (619) 661-1055 www.sanyovideo.com tdk (847) 803-6100 (847) 803-6296 www.component.tdk.com murata usa: usa: www.murata.com (814) 237-1431 (814) 238-0490 (800) 831-9172 taiyo yuden (408) 573-4150 (408) 573-4159 www.t-yuden.com applications where v out > 4.3v due to the very high slew rates associated with the switch nodes, schottky diode clamps are required in any applica- tion where v out can exceed 4.3v to prevent the switch
LTC3425 19 3425f applicatio s i for atio wu uu l1 2.7 h c in 2.2 f r lim 75k r t 12.1k l2 2.7 h l3 2.7 h l4 2.7 h d4 c in : taiyo yuden jmk107bj225ma c s : taiyo yuden lmk107bj474ka c out : taiyo yuden jmk212bj475mg ( 4) c bulk : avx tpsd157m006r0050 v in v out swa v in 3.3v swb LTC3425 swc swd sgnd shdn v outs v outa v outb v outc v outd refout ccm refen syncin burst r t i lim pgood syncout ss fb comp gnda gndb gndc gndd c2 220pf 3425 f07 c out 4.7 f 4 c ss 0.01 f c s 0.47 f 2 q1 c bulk 150 f 6.3v r3 100k r2 309k r4 100k pgood r1 100k v out 5v 2.5a + d3 d2 d1 d1 to d4: motorola mbr0520l l1 to l4: tdk rlf5018t-2r7m1r8 q1: zetex zxm61p02f l1 2.7 h c in 2.2 f r lim 75k r t 12.1k l2 2.7 h l3 2.7 h l4 2.7 h d4 c in : taiyo yuden jmk107bj225ma c out : taiyo yuden jmk212bj475mg ( 4) c bulk : avx tpsd157m006r0050 v in v out swa v in 3.3v swb LTC3425 swc swd sgnd shdn v outs v outa v outb v outc v outd refout ccm refen syncin burst r t i lim pgood syncout ss fb comp gnda gndb gndc gndd c2 220pf 3425 f08 c out 4.7 f 4 c ss 0.01 f c bulk 150 f 6.3v r3 100k r2 309k r4 100k pgood r1 100k v out 5v 2.5a + d3 d2 d1 d1 to d4: motorola mbr0520lt1 l1 to l4: tdk rlf5018t-2r7m1r8 figure 7. application circuit for v out > 4.3v with inrush limiting and output disconnect figure 8. application circuit for v out > 4.3v when inrush limiting and output disconnect are not required
LTC3425 20 3425f modulator control to output dc gain, and the error amp open-loop gain gives the dc gain of the system: gg g v v g v i g dc controloutput ea ref out control in out ea = =? ,, 8 5 000 the output filter pole is given by: f i vc filterpole out out out = p where c out is the output filter capacitor. the output filter zero is given by: f rc filterzero esr out = p 1 2 where r esr is the output capacitor equivalent series resistance. a troublesome feature of the boost regulator topology is the right half plane zero (rhp), and is given by: f v il rhpz in out = p 2 2 at heavy loads this gain increase with phase lag can occur at a relatively low frequency. the loop gain is typically rolled off before the rhp zero frequency. the typical error amp compensation is shown in figure 9. the equations for the loop dynamics are as follows: f ec which is extremely close to dc f rc f rc pole c zero zc pole zc 1 6 1 1 1 2 2 1 2 100 1 2 1 2 ? p = p = p + fb 1.25v v out r1 r2 3425 f09 r z v c c c1 c c2 error amp figure 9 applicatio s i for atio wu uu
LTC3425 21 3425f typical applicatio s u single or dual cell to 3.3v boost with automatic burst mode operation l1 2.2 h c in 2.2 f c3 0.056 f r lim 75k r t 15k r4 20k l2 2.2 h l3 2.2 h l4 2.2 h c bulk : avx tpsd157m004r0050 c in : taiyo yuden jmk107bj225ma v in swa v in = 1.1v to 3v swb LTC3425 swc swd sgnd shdn v outs v outa v outb v outc v outd refout ccm refen syncin burst r t i lim pgood syncout ss fb comp gnda gndb gndc gndd + c2 220pf 3425 ta03 c out 4.7 f 4 c ss 0.01 f r3 100k r2 511k r5 10k c1 22pf r5 100k c bulk 150 f 4v pgood r1 301k v out 3.3v 1a + c out : taiyo yuden jmk212bj475mg ( 4) l1 to l4: murata lqh4c2r2m04
LTC3425 22 3425f application with user commanded burst mode operation and buffered reference output enabled l1 3.3 h c in 2.2 f c1 0.1 f r lim 75k r t 30.1k burst pwm l2 3.3 h l3 3.3 h l4 3.3 h c in : taiyo yuden jmk107bj225ma c out : taiyo yuden jmk212bj475mg ( 4) l1 to l4: sumida cdrh4d28 v in v out v ref swa v in = 1.8v to 3v swb LTC3425 swc swd sgnd shdn v outs v outa v outb v outc v outd refout ccm refen syncin burst r t i lim pgood syncout ss fb comp gnda gndb gndc gndd + c2 330pf 3425 ta04 c out 4.7 f 4 c ss 0.01 f r3 33k r2 511k r4 100k pgood r1 301k v out 3.3v 2a r4 10k c3 22pf typical applicatio s u
LTC3425 23 3425f package descriptio u uh package 32-lead plastic qfn (5mm 5mm) (reference ltc dwg # 05-08-1693) 5.00 0.10 (4 sides) note: 1. drawing proposed to be a jedec package outline m0-220 variation whhd-(x) (to be approved) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated pin 1 top mark 0.40 0.10 31 1 2 32 bottom view?xposed pad 3.45 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.23 0.05 (uh) qfn 0102 0.50 bsc 0.200 ref 0.00 ?0.05 0.57 0.05 3.45 0.05 (4 sides) 4.20 0.05 5.35 0.05 0.23 0.05 package outline 0.50 bsc recommended solder pad layout information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC3425 24 3425f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com ? linear technology corporation 2003 lt/tp 0803 1k printed in usa typical applicatio u 10mhz, high current, very low profile, 8-phase converter using two LTC3425s operating in fixed frequency mode with forced ccm (max component height = 1.6mm) l5 1 h c in2 2.2 f r6 75k r t2 14.7k r f4 17.4k r f3 10.2k l6 1 h l7 1 h l8 1 h c in1,2 : taiyo yuden jmk107bj225ma c out : taiyo yuden jmk212bj475mg ( 8) l1 to l8: murata lqh32cn1r0m51 v in swa swb LTC3425 swc swd sgnd shdn v outs v outa v outb v outc v outd refout ccm refen syncin burst r t i lim pgood syncout ss fb comp gnda gndb gndc gndd c1 330pf 3425 ta05 c out2 4.7 f 4 c ss 0.022 f r3 33k r f2 17.4k r4 100k pgood r f1 10.2k v out 3.3v 5a l1 1 h c in1 2.2 f r5 75k r t1 12.1k l2 1 h l3 1 h l4 1 h v in v out v in 2.5v swa swb LTC3425 swc swd sgnd shdn v outs v outa v outb v outc v outd refout ccm refen syncin burst r t i lim pgood syncout ss fb comp gnda gndb gndc gndd c out1 4.7 f 4 v out related parts part number description comments lt ? 1370/lt1370hv 6a (i sw ) 500khz, high efficiency step-up dc/dc v in : 2.7v to 30v, v out(max) : 35v/42v, i q : 4.5ma, i sd : <12 m a, converters dd, to220-7 lt1371/lt1371hv 3a (i sw ) 500khz, high efficiency step-up dc/dc v in : 2.7v to 30v, v out(max) : 35v/42v, i q : 4ma, i sd : <12 m a, converters dd, to220-7, s20 lt1613 550ma (i sw ) 1.4mhz, high efficiency step-up dc/dc 90% efficiency, v in : 0.9v to 10v, v out(max) : 34v, i q : 3ma, converter i sd : <1 m a, thinsot lt1618 1.5a (i sw ) 1.25mhz, high efficiency step-up dc/dc 90% efficiency, v in : 1.6v to 18v, v out(max) : 35v, i q : 1.8ma, converter i sd : <1 m a, ms10 ltc1700 no r sense tm 530khz, synchronous step-up 95% efficiency, v in : 0.9v to 5v, i q : 200 m a, i sd : <10 m a, ms10 dc/dc controller ltc1871 wide input range, 1mhz, no r sense current mode boost, 92% efficiency, v in : 2.5v to 36v, i q : 250 m a, i sd : <10 m a, ms10 flyback and sepic controller lt1930/lt1930a 1a (i sw ) 1.2mhz/2.2mhz, high efficiency step-up dc/dc high efficiency, v in : 2.6v to 16v, v out(max) : 34v, i q : 4.2ma/5.5ma, converters i sd : <1 m a, thinsot lt1946/lt1946a 1.5a (i sw ) 1.2mhz/2.7mhz, high efficiency step-up high efficiency, v in : 2.45v to 16v, v out(max) : 34v, i q : 3.2ma, dc/dc converters i sd : <1 m a, ms8 lt1961 1.5a (i sw ) 1.25mhz, high efficiency step-up dc/dc 90% efficiency, v in : 3v to 25v, v out(max) : 35v, i q : 0.9ma, converter i sd : 6 m a, ms8e ltc3400/ltc3400b 600ma (i sw ) 1.2mhz, synchronous step-down dc/dc 92% efficiency, v in : 0.85v to 5v, v out(max) : 5v, i q : 19 m a/300 m a, converters i sd : <1 m a, thinsot ltc3401/ltc3402 1a/2a (i sw ) 3mhz, synchronous step-up dc/dc 97% efficiency, v in : 0.5v to 5v, v out(max) : 6v, i q : 38 m a, i sd : <1 m a, converters ms10 ltc3701 2-phase, 550khz, low input voltage, dual step-down 97% efficiency, v in : 2.5v to 10v, i q : 460 m a, i sd : <9 m a, ssop-16 dc/dc controller

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